The invention relates to a multi-channel digital/analog converter arrangement.
A digital/analog converter, for short also called D/A converter in the text which follows, is designed for converting a digital, for example a binary input signal into an analog output signal, for example an output voltage or an output current. Regarding the general background of D/A converters, reference is made to U.S. Pat. Nos. 6,346,901 B1, 4,712,091 and 5,293,166.
D/A converters are mainly used in digital signal processing. Applications for digital signal processing are, for example computer- and software-based applications, for example in a microprocessor, or telecommunication applications, for example broadband applications or mobile radio applications. In modern systems of digital signal processing there is an increasing requirement for processing greater and greater volumes of data in shorter and shorter time. With the advancing development in the field of integrated circuits and the further development of modern communication systems, the capability of these systems for processing data at high data rate also increases. Modern data communication systems are operated, for example, at an operating frequency of about 4 GHz and more. To provide effective data processing, however, it is very essential to forward the processed data, and to convert them into analog output signals, at corresponding speed.
To implement these very high-quality systems of digital signal processing, D/A converters are therefore increasingly used which provide high-bit-rate digital/analog conversion with a very high sampling rate and the best possible analog characteristics, if possible. The quality and accuracy of the D/A conversion plays a decisive role in this context. In the text which follows, such D/A converters will be called high-speed D/A converters.
The digital data to be converted into an analog output signal by the high-speed D/A converter come from a data source, for example from a memory chip, a logic circuit, a microprocessor or the like. To be able to process the large volumes of data to be processed, a number of data sources are frequently used. In this arrangement, the data are read out of the various data sources in parallel and supplied to a corresponding processing device for conversion into an analog output signal. One of these data sources and the corresponding downstream data path in each case define one data channel, the different data channels being arranged in parallel with one another. The corresponding D/A converter will be called a multi-channel D/A converter in the text which follows. To combine the various data channels, a multiplexer device is provided which generates from the data of the various data channels a single digital data stream which is then supplied to the downstream digital/analog converter. When the data speed is very high, very high demands are made on the multiplexing of the data of the various data channels.
In published Japanese application for patents 01099323 and 04016024, digital/analog converter circuits are in each case described in which the data of a number of parallel data channels are coupled into a corresponding combining circuit such as, for example, a multiplexer and are output as serial digital data stream which is then supplied to the digital/analog converter. Although the use of a number of parallel data channels which in each case have a comparatively low data rate allows the data processing to be arranged in a simpler manner there, the problem still exists that, in particular, in the multiplexer and on the data path between the multiplexer and the digital input of the downstream digital/analog converter, the data present there has a very high data rate and thus also has to be processed further with a correspondingly high speed. A high data processing speed in these elements is, therefore, associated with a correspondingly high power consumption. At very high data processing speeds, signal conditioning must also be performed following the multiplexer, in which so-called retiming is performed. In this process, the switching edges of the data signal combined by multiplexing are adjusted to the corresponding requirements of the current switches of the downstream digital/analog converter. At very high data rates, in particular or at very high volumes of data to be processed, respectively, it is also no longer possible in many applications to combine these volumes of data in the multiplexer.
A further possibility for processing a large volume of data is the provision of a number of parallel digital/analog converters which are in each case allocated to one data channel. This multiplicity of digital/analog converters is designed for converting the data of an in each case associated data channel into an analog signal so that a number of analog output signals corresponding to the multiplicity of digital/analog converters is present. These output signals can then be combined into a single analog signal in an analog multiplexer provided especially for this purpose. Such an arrangement which thus has a number of digital/analog converters and an analog multiplexer is described, for example, in the article by M. Clara et al.: “A 350 MHz low-OSR SD Current-Steering DAC with Active Termination in 0.13 μm CMOS”, ISSCC 2005, pages 118-119, particularly in FIG. 1. The disadvantage of the arrangement described there consists in that a multiplicity of individual digital/analog converters must be provided for the D/A conversion which entails considerable circuit expenditure, particularly if there are many data channels.